Components of a Computer: Processor Components - Complete Study Guide

OCR A Level Computer Science (H446) · Computer Systems

Last Updated: June 2026 Suitable for: OCR A Level Computer Science (H446) Study Time: 4-6 hours Exam Weight: Section 1.1 (Components of a computer) is examined in Paper 1 (H446/01 Computer Systems, 140 marks, 40% of the A Level) Specification Reference: OCR H446 — 1.1.1 Structure and function of the processor

Note: Processor components are the foundation of the whole H446/01 paper. The CPU, the buses, the fetch-decode-execute cycle and the von Neumann model reappear in pipelining, performance, assembly language and architecture questions. Examiners reward precise register names and exact transfers (which register feeds which bus), not vague descriptions. Learn the five core registers and the cycle as a sequence of register transfers and you protect marks across the entire processor topic.

LEARNING OBJECTIVES

By the end of this chapter, you will be able to:

Foundation (every student must secure these)

• Name the three main parts of the CPU: the ALU, the Control Unit and the registers
• State the purpose of each special-purpose register: PC, ACC, MAR, MDR and CIR
• Describe the role of the ALU and the Control Unit
• Identify the three system buses (address, data, control) and what each carries
• List the stages of the fetch-decode-execute cycle in the correct order
• Define the stored program concept

Higher (stretch for the A/A* grades)

• Describe the fetch-decode-execute cycle as a precise sequence of register transfers
• Explain how the width of the address bus and data bus affects addressable memory and performance
• Compare von Neumann and Harvard architectures and justify where each is used
• Explain why the address bus is unidirectional but the data bus is bidirectional
• Link clock speed, bus width and word length to overall processor performance

PART 1: STUDY MATERIAL

1.1 THE CPU AND ITS MAIN COMPONENTS

Definition: The Central Processing Unit (CPU) is the component that fetches, decodes and executes the instructions of a program. It is built from three main parts: the Arithmetic Logic Unit (ALU), the Control Unit (CU) and a set of registers.

Key Points:

• The ALU carries out all arithmetic operations (add, subtract, multiply) and all logical operations (AND, OR, NOT, comparisons). It also performs the bit-shift operations used in multiplication and division.
• The Control Unit (CU) directs the operation of the processor. It decodes each instruction, manages the flow of data along the buses and sends control signals to coordinate the other components in time with the clock.
• Registers are tiny, extremely fast on-chip storage locations that hold the data and addresses the CPU is working on right now. They are faster than cache or main memory because they are inside the CPU itself.
• The CU uses the system clock to synchronise everything; one tick of the clock steps the processor through its operations.

Why This Matters: Almost every processor question begins by assuming you can name these three parts and say what each does. Confusing the ALU (does the calculation) with the CU (decodes and coordinates) is a frequent and avoidable error.

Example: When a program executes an ADD, the CU decodes the instruction and signals the ALU; the ALU performs the addition; the result is placed in the Accumulator (ACC) register.

Common Misconception: "Registers and RAM are the same thing." Registers are inside the CPU and hold only a word or two; RAM (main memory) is separate, much larger and much slower. The CPU constantly moves data between RAM and its registers over the buses.

Examiner Tips — Section 1.1

• Spell out the role: ALU = arithmetic and logic; CU = decode instructions and send control signals.
• Do not write "the CPU calculates" when a question wants the ALU specifically.

1.2 THE SPECIAL-PURPOSE REGISTERS

Definition: A register is a small, fast storage location within the CPU. OCR H446 requires five specific special-purpose registers, each with a defined job in the fetch-decode-execute cycle.

Key Points: Learn each register by its full name, abbreviation and exact role:

• The MAR and MDR are the CPU's link to memory: the MAR puts an address onto the address bus, the MDR sends/receives data on the data bus.
• The PC is incremented during the fetch stage so it always points to the next instruction (before any jump is applied).
• A General Purpose Register (GPR) can hold any data the program needs; a special-purpose register (the five above) has one fixed job.

Why This Matters: The exact wording matters. "MAR holds the address, MDR holds the data" is a one-mark statement examiners look for verbatim. Mixing up MAR and MDR is the single most common mistake in this topic.

Common Misconception: "The MDR only holds data, never instructions." During the fetch stage the MDR holds the instruction copied from memory before it moves to the CIR — it carries whatever was at that address, data or instruction.

Examiner Tips — Section 1.2

• Memorise the pairing: MAR ↔ address bus, MDR ↔ data bus.
• If asked "which register points to the next instruction?" the answer is always the PC.

1.3 THE SYSTEM BUSES

Definition: A bus is a set of parallel wires that transfers data, addresses or control signals between the CPU, memory and input/output. The three system buses are the address bus, the data bus and the control bus.

Key Points:

• The address bus is unidirectional because only the CPU specifies which location to access — addresses never travel back to the CPU.
• The data bus is bidirectional because data must flow both ways: into the CPU when reading, out of the CPU when writing.
• The control bus carries individual signal lines such as memory read, memory write, clock and interrupt request.

Why This Matters: Bus questions test direction (which way data flows) and width (how performance is affected). Getting the direction of the address bus and data bus the wrong way round is a classic lost mark.

Common Misconception: "All three buses are bidirectional." Only the data bus and control bus carry signals in both directions; the address bus is one-way from the CPU.

Examiner Tips — Section 1.3

• Justify direction: address bus one-way because only the CPU issues addresses; data bus two-way because data is both read and written.

1.4 BUS WIDTH AND PERFORMANCE

Definition: Bus width is the number of parallel wires (bits) a bus has, which sets how many bits can be transferred at once.

Key Points:

• The width of the data bus determines how many bits can be moved per transfer. A wider data bus moves more data per clock cycle, improving performance.
• The width of the address bus determines how many distinct memory locations can be addressed. An n-bit address bus can address 2ⁿ locations.
• Example: a 16-bit address bus can address 2¹⁶ = 65 536 locations; a 32-bit address bus can address 2³² ≈ 4.3 billion locations.
• A wider data bus that matches the word length lets a whole word be fetched in one transfer rather than several, reducing the number of memory accesses.

Why This Matters: Performance questions ask you to link bus width to a concrete effect: more addressable memory (address bus) or more data per transfer (data bus). Vague answers like "it's faster" score nothing without the cause.

Example: Doubling the data bus from 16 to 32 bits lets the CPU fetch a 32-bit instruction in a single transfer instead of two, halving the memory accesses for that fetch.

Common Misconception: "Widening the address bus speeds up data transfer." No — the address bus width affects how much memory can be addressed, not how fast data moves. Data transfer rate depends on the data bus width (and clock speed).

Examiner Tips — Section 1.4

• Address bus width → amount of addressable memory (2ⁿ locations).
• Data bus width → amount of data per transfer (throughput/performance).

1.5 THE FETCH-DECODE-EXECUTE CYCLE

Definition: The fetch-decode-execute (FDE) cycle is the repeating sequence the CPU follows to process each instruction: fetch it from memory, decode what it means, then execute it.

Key Points (the three stages):

The cycle, written as a sequence of register transfers:

FETCH
  MAR  <- [PC]              ; address of next instruction copied to MAR
  PC   <- [PC] + 1          ; program counter incremented
  MDR  <- [memory[MAR]]     ; instruction at that address read on data bus into MDR
  CIR  <- [MDR]             ; instruction copied to the Current Instruction Register

DECODE
  Control Unit decodes the instruction held in the CIR
  (splits it into opcode + operand)

EXECUTE
  The instruction is carried out; e.g. for an ADD the ALU
  computes the result and stores it: ACC <- [ACC] + operand

• The PC is incremented during fetch, so it points at the next instruction even before the current one finishes.
• A jump/branch instruction changes the PC during execute, so the next fetch comes from a different address.
• The control bus signals memory read during fetch and memory write when storing results.

Why This Matters: Higher-mark questions ask for the cycle "in terms of register transfers". The notation above (which register receives from which, and when the PC is incremented) is exactly what earns full marks.

Common Misconception: "The PC is incremented at the end of the cycle." It is incremented during the fetch stage, immediately after its value is copied to the MAR — not after execute.

Examiner Tips — Section 1.5

• Always show MAR <- PC, then PC incremented, then MDR <- memory, then CIR <- MDR.
• State that a jump alters the PC in the execute stage, redirecting the next fetch.

1.6 THE VON NEUMANN ARCHITECTURE

Definition: The von Neumann architecture is a processor design in which a single memory and a single bus system store and transfer both instructions and data, and instructions are executed sequentially.

Key Points:

• Instructions and data share the same memory and the same buses.
• Because instructions and data travel on the same data bus, only one can be fetched at a time — this bottleneck is the von Neumann bottleneck.
• It uses the five registers and the FDE cycle described above.
• Most general-purpose computers (PCs, servers) use a von Neumann (or modified von Neumann) design because it is simpler and more flexible.

Why This Matters: Comparison questions reward you for naming the shared-memory feature and identifying the bottleneck it creates, then contrasting it with Harvard.

Common Misconception: "Von Neumann machines store data and instructions in separate memories." That is Harvard. Von Neumann uses one shared memory.

Examiner Tips — Section 1.6

• Key phrase: shared memory and shared bus for instructions and data → causes the von Neumann bottleneck.

1.7 THE HARVARD ARCHITECTURE

Definition: The Harvard architecture is a processor design with physically separate memories and buses for instructions and for data, allowing both to be accessed simultaneously.

Key Points:

• Separate instruction memory and data memory, each with its own bus.
• Instructions and data can be fetched at the same time, removing the von Neumann bottleneck and improving throughput.
• More complex and more expensive to build because it needs two memory systems and two bus systems.
• Common in embedded systems and Digital Signal Processors (DSPs), where predictable, high-speed instruction/data access matters.
• Many modern CPUs are modified Harvard: separate instruction and data caches but a single main memory.

Why This Matters: OCR expects a balanced comparison: Harvard is faster (parallel access) but more costly and less flexible; von Neumann is simpler and cheaper but has a bottleneck.

Common Misconception: "Harvard is always better." It is faster for parallel access but more expensive and less flexible; the right choice depends on the application.

Examiner Tips — Section 1.7

• Trade-off answer: Harvard = parallel access, faster, but costlier and more complex.

1.8 THE STORED PROGRAM CONCEPT

Definition: The stored program concept is the principle that program instructions are stored in main memory alongside data, and are fetched and executed sequentially by the processor.

Key Points:

• Both the program (instructions) and the data it works on are held in the same main memory as binary values.
• Because instructions are stored as data, the machine is general purpose: loading a different program changes what the computer does, with no rewiring.
• Instructions are normally executed in sequence, address by address, unless a jump/branch changes the PC.
• This concept underpins the von Neumann architecture and the whole FDE cycle.

Why This Matters: This is the founding idea of the modern programmable computer. A common one-mark definition question asks you to state it precisely: instructions and data stored together in memory and fetched in sequence.

Common Misconception: "Stored program just means saving a file to disk." It specifically means instructions are held in main memory as binary and fetched/executed by the CPU — not long-term file storage.

Examiner Tips — Section 1.8

• Definition to memorise: instructions and data are stored together in memory and executed sequentially.

PART 2: WORKED EXAMPLES

Example 1: Matching Registers to Roles

Question: State which register (PC, MAR, MDR, CIR or ACC) does each job: (a) holds the address of the next instruction; (b) holds the result of an ALU calculation; (c) holds the instruction currently being decoded; (d) holds data just read from memory.

Solution: (a) PC — Program Counter holds the address of the next instruction. (b) ACC — the Accumulator stores ALU results. (c) CIR — the Current Instruction Register holds the instruction being decoded/executed. (d) MDR — the Memory Data Register holds data (or an instruction) read from memory.

Examiner Tip: Watch parts (c) and (d) — candidates often swap MDR and CIR. The MDR is the transit register for the data bus; the CIR holds the instruction once it is ready to decode.

Example 2: The Fetch Stage as Register Transfers

Question: Describe the fetch stage of the FDE cycle in terms of register transfers.

Solution:

MAR <- [PC]            ; copy the address of the next instruction into the MAR
PC  <- [PC] + 1        ; increment the program counter
MDR <- [memory[MAR]]   ; read the instruction at MAR over the data bus into the MDR
CIR <- [MDR]           ; copy the instruction into the Current Instruction Register

The Control Unit asserts the memory read line on the control bus while this happens.

Examiner Tip: Show the PC increment immediately after MAR <- PC. Stating it happens "during fetch" (not after execute) is a frequent mark discriminator.

Example 3: Address Bus Width and Addressable Memory

Question: A computer has a 20-bit address bus. (a) How many memory locations can it address? (b) The address bus is widened to 24 bits. By what factor does the addressable memory increase?

Solution: (a) 2²⁰ = 1 048 576 locations (1 MiB if each location is one byte). (b) Going from 2²⁰ to 2²⁴ multiplies the addressable space by 2⁴ = 16 times.

Examiner Tip: Address bus width affects how much memory can be addressed (2ⁿ), never the speed of data transfer — that is the data bus.

Example 4: Data Bus Width and Performance

Question: A processor with a 16-bit data bus fetches a 32-bit instruction. Explain how many memory transfers this needs, and how doubling the data bus to 32 bits would help.

Solution: A 16-bit data bus moves 16 bits per transfer, so a 32-bit instruction needs two transfers. With a 32-bit data bus the whole instruction is fetched in one transfer, halving the memory accesses for the fetch and so improving performance (fewer accesses per instruction).

Examiner Tip: Link bus width to a concrete count of transfers. "It's faster" alone scores nothing; "one transfer instead of two" earns the mark.

Example 5: Comparing Von Neumann and Harvard

Question: Compare the von Neumann and Harvard architectures, giving one advantage of each.

Solution:

• Von Neumann: one shared memory and bus system for instructions and data. Advantage: simpler and cheaper to build; flexible use of memory. Drawback: the von Neumann bottleneck — instructions and data cannot be fetched at the same time.
• Harvard: physically separate memories and buses for instructions and data. Advantage: instructions and data can be accessed simultaneously, giving higher throughput. Drawback: more complex and expensive. Von Neumann suits general-purpose computers; Harvard suits embedded systems and DSPs.

Examiner Tip: A "compare" answer needs the same feature judged for both architectures (e.g. simultaneous access: Harvard yes, von Neumann no) plus a stated trade-off.

Example 6: Explaining Bus Direction

Question: Explain why the address bus is unidirectional but the data bus is bidirectional.

Solution: The address bus is unidirectional because only the CPU ever issues an address to specify which memory or I/O location to access; addresses are never sent back to the CPU. The data bus is bidirectional because data must travel into the CPU when a location is read and out of the CPU when a location is written, so it must carry signals in both directions.

Examiner Tip: Anchor the explanation in who issues what: addresses come only from the CPU (one way); data is both read and written (two way).

APPENDIX A: QUICK REFERENCE

The Five Registers

The Three Buses

Fetch-Decode-Execute (key transfers)

MAR <- [PC]
PC  <- [PC] + 1
MDR <- [memory[MAR]]
CIR <- [MDR]
DECODE (Control Unit)  ->  EXECUTE (ALU / data move / jump)

Architecture Comparison

Performance Links

• Address bus width → addressable memory (2ⁿ).
• Data bus width → data per transfer (throughput).
• Clock speed → cycles per second (more FDE cycles per second).
• Word length matched to data bus → fewer transfers per instruction.

APPENDIX B: GLOSSARY

Accumulator (ACC): A register that stores the result of calculations performed by the ALU.

Address bus: A unidirectional bus carrying the address of the memory or I/O location to be accessed.

ALU (Arithmetic Logic Unit): The CPU component that performs all arithmetic and logical operations.

Bus: A set of parallel wires transferring data, addresses or control signals between components.

Bus width: The number of bits (wires) a bus can carry simultaneously.

Control bus: A bidirectional bus carrying control and timing signals such as read, write, clock and interrupt.

Control Unit (CU): The CPU component that decodes instructions and issues control signals to coordinate the processor.

CIR (Current Instruction Register): A register holding the instruction currently being decoded and executed.

CPU (Central Processing Unit): The component that fetches, decodes and executes program instructions.

Data bus: A bidirectional bus carrying data or instructions to and from memory.

Fetch-decode-execute cycle: The repeating sequence by which the CPU processes each instruction.

General Purpose Register (GPR): A register that can hold any data the program is working with.

Harvard architecture: A design with separate memories and buses for instructions and data, allowing simultaneous access.

MAR (Memory Address Register): A register holding the address of the memory location to be read or written.

MDR (Memory Data Register): A register holding the data or instruction being transferred to or from memory.

Program Counter (PC): A register holding the address of the next instruction to be fetched.

Register: A small, very fast storage location inside the CPU.

Stored program concept: The principle that instructions and data are stored together in main memory and executed sequentially.

System clock: A timing signal that synchronises the operations of the processor.

Von Neumann architecture: A design using a single shared memory and bus for both instructions and data.

Von Neumann bottleneck: The performance limit caused by instructions and data sharing one bus, so only one can be fetched at a time.

Word length: The number of bits the CPU handles as a single unit.

Document created: June 2026 For: OCR A Level Computer Science (H446) · Computer Systems Study time: 4-6 hours Specification reference: 1.1.1 Structure and function of the processor

Next Chapter: Chapter 2 - Types of Processor

Premium lesson expansion: Components of a Computer: Processor Components - Complete Study Guide

What a top student must understand

Computer Science answers should be technical and operational. Define the component or concept, describe how it works step by step, then apply it to performance, security, memory, data integrity or maintainability.

OCR H446-style precision: use correct technical vocabulary, trace algorithms and justify design trade-offs.

The key move is to connect knowledge -> context -> consequence -> judgement. Do not leave the idea as a definition. Turn it into a working explanation that could answer a real exam question.

Guided walkthrough

Worked method: trace the input, process and output. For algorithms, run a dry trace table. For systems questions, explain the role of each component and the consequence of changing it.

Now apply that method to Components of a Computer: Processor Components - Complete Study Guide:

1. Identify the exact command word.
2. Select the relevant knowledge or method.
3. Use one detail from the lesson, data, diagram, extract or case.
4. Build at least two linked consequences.
5. Add a limitation, comparison or judgement if the mark tariff requires it.

Examiner-style insight

Middle-grade answers usually know the topic but do not control the answer. Higher-grade answers make the reasoning visible. They use precise vocabulary, apply the idea to the specific context and avoid unsupported general statements. If the question gives evidence, quote or use it. If it asks for evaluation, decide what the answer depends on.

Common misconceptions to avoid

• Using storage and memory as if they are identical.
• Describing encryption as compression.
• Writing code logic without considering boundary cases or validation.

Worked example

Prompt: Explain why a student could lose marks on a question about Components of a Computer: Processor Components - Complete Study Guide even if they remember the key definition.

Model answer: A definition alone may only show basic knowledge. To reach the higher levels, the answer must apply the idea to the specific context and explain the consequence. For example, a strong answer would use a detail from the question, link it to the relevant process or decision, and then explain why that effect matters. If the question is evaluative, it should also include a supported judgement rather than a one-sided claim.

Why this works: The answer shows knowledge, application and analysis. It also explains the examiner's likely reason for withholding marks: the missing link between recall and applied reasoning.

Resource-tab notes to add to revision

• Trace-table checklist: variables, initial values, loop condition, final output.
• Security notes: threat, vulnerability, control, limitation.
• Programming habit: state data type, validation rule and test case.

Memory aid

Use KACJ: Knowledge, Application, Chain of reasoning, Judgement. Before submitting an answer, check that all four parts are present where the question demands them.

MCQ mini-bank

1. Which answer best shows premium understanding of Components of a Computer: Processor Components - Complete Study Guide?

   • A. A memorised definition with no context
   • B. A clear idea applied to evidence or a named example
   • C. A long paragraph that repeats the question
   • D. A judgement with no supporting reason
   • Correct: B. Explanation: examiners reward accurate knowledge used in context, not isolated recall.

2. Trace a short algorithm and identify the final output.

   • A. It names a keyword only
   • B. It gives a sequence, reason or consequence
   • C. It ignores the command word
   • D. It replaces evidence with opinion
   • Correct: B. Explanation: strong answers make the cause-and-effect chain visible.

3. Explain one trade-off between performance and security.

   • A. Use the data or case evidence directly
   • B. Write a generic paragraph
   • C. Skip the calculation or source
   • D. Repeat the definition twice
   • Correct: A. Explanation: application marks depend on the specific information in front of you.

4. Which mistake most often caps an answer on this topic?

   • A. Giving a precise example
   • B. Using the correct subject vocabulary
   • C. Making a claim without explaining why it matters
   • D. Writing a final judgement
   • Correct: C. Explanation: unsupported claims do not build analysis.

5. In a A-Level extended response, what should the final sentence do?

   • A. Introduce a brand-new topic
   • B. Repeat the first sentence exactly
   • C. Make a supported judgement linked to the question
   • D. Apologise for uncertainty
   • Correct: C. Explanation: the final judgement should answer the command word and weigh evidence.

6. Evaluate whether a proposed system design is suitable for the user requirements.

   • A. A one-sided assertion
   • B. A balanced answer with evidence and a depends-on factor
   • C. A list of facts
   • D. A copied phrase from the question
   • Correct: B. Explanation: higher grades come from weighing evidence, not just naming it.

Long-answer practice

4 marks: Explain one core idea from Components of a Computer: Processor Components - Complete Study Guide. Use one precise piece of evidence, vocabulary or context.

6 marks: Analyse one consequence or effect linked to Components of a Computer: Processor Components - Complete Study Guide. Your answer should contain at least two connected steps.

8/9 marks: Assess how important one factor is in this topic. Use evidence and a short judgement.

12/16/25 marks where relevant: Evaluate the statement: "Components of a Computer: Processor Components - Complete Study Guide is best understood through one main factor." Build two developed arguments, include a limitation and finish with a supported judgement.

Mark-scheme style guidance

• Award lower credit for accurate but isolated knowledge.
• Award middle credit for explanation with some application.
• Award high credit for a developed chain that uses precise evidence and answers the command word.
• For the top band, require a judgement that compares importance, scale, reliability, cost, context or long-term impact.

Stretch and challenge

Create a new exam question for this topic using a different context, figure, extract or scenario. Then write a model answer and annotate it with AO1/AO2/AO3/AO4 or the equivalent subject skills. This turns revision into examiner thinking rather than rereading.

Gold Standard Exam Mastery: Components of a Computer: Processor Components

Specification mapping

OCR A-Level Computer Science H446: computer systems, algorithms and programming, plus the programming project.

Exam-board lens for this lesson: OCR. Use this chapter to revise the content, but also to practise how examiners reward marks in real papers.

Assessment objective map

• AO1: demonstrate technical knowledge of systems, algorithms and programming concepts.
• AO2: apply knowledge to scenarios, code, data structures and computational problems.
• AO3: analyse, design, evaluate and refine solutions, especially in algorithms and project-style contexts.
• Project thinking: problem analysis, decomposition, success criteria, testing and evaluation.

Command words to practise

explain, describe, trace, write, compare, evaluate

What examiners reward

• In Paper 1, connect architecture or systems concepts to performance, security or reliability.
• In Paper 2, trace algorithms accurately and justify design decisions.
• For project-style answers, define measurable success criteria and test against edge cases.

Common mistakes to avoid

• Using everyday computing language instead of precise OCR technical vocabulary.
• Explaining intended algorithm behaviour rather than tracing actual state changes.
• Evaluating a solution without criteria, evidence or limitations.

Answer quality ladder

Grade 4 / basic pass move: States a correct technical fact or traces a simple step.

Grade 7 / strong answer move: Applies the concept to a scenario and explains consequences.

Grade 9 or A move:* Designs, analyses and evaluates a robust computational solution with precise evidence.

Exam-style practice prompts

• Trace a short algorithm linked to Components of a Computer: Processor Components and record each variable state.
• Write a design decision with justification and a testing implication.
• Evaluate a technical solution using performance, security, maintainability or usability.

Mark scheme guidance

For short answers, make the point precise before adding explanation. For extended answers, build a chain of reasoning, apply it to the named context, then make a judgement only if the command word requires one. A high-mark answer is not just longer; it is more selective, better evidenced and more explicit about why one factor matters more than another.

Topic-specific teaching upgrade

• Computer Science answers must separate what a system is, how it works and why the design choice matters.
• Algorithm questions reward tracing actual state changes. Intentions do not matter if the variable values or control flow produce a different output.
• Evaluation should use criteria such as correctness, time complexity, space use, maintainability, security, portability and user impact.

Worked example or model move

• Trace routine: list initial values, update only when the code does, record loop conditions and write the final output exactly.
• Design routine: define inputs, processing, outputs, validation, boundary cases and tests before writing code.

Examiner-method focus for this lesson

• Use technical vocabulary: cache, register, opcode, fetch-decode-execute, abstraction, encapsulation, normalisation, hashing or encryption only when accurate.
• For SQL/database answers, keep entities, attributes, keys and relationships distinct.
• For ethics/legal answers, name the stakeholder, risk, law or principle and consequence.

Original long-answer practice

• Evaluate a design choice linked to Components of a Computer: Processor Components using at least three technical criteria.
• Trace or design an algorithm for Components of a Computer: Processor Components, including boundary-case testing.

Repair-set misconception tags

• algorithm_trace
• technical_vocabulary
• system_evaluation
• testing_edge_cases

Board-aware exam routine

1. Identify whether the question tests recall, tracing, coding, systems explanation or evaluation.
2. Use exact technical vocabulary and avoid everyday wording.
3. For algorithms, trace actual values step-by-step before explaining purpose.
4. For evaluations, judge against criteria: correctness, efficiency, maintainability, security and usability.

Model answer builder

• Opening move: name the exact concept, method, text, process, model or argument being tested.
• Evidence move: add data, quotation, calculation, example, case detail, code trace, source detail or diagram feature.
• Development move: explain the link in a full chain, not a loose comment.
• Precision move: use exam vocabulary from this lesson and avoid vague filler.
• Judgement move: only where the command word requires it, decide which factor, method, interpretation or option is strongest and why.

Stored MCQ and retrieval design

1. Easy: State or identify one core idea from Components of a Computer: Processor Components.
2. Medium: Explain how Components of a Computer: Processor Components works in a specific exam-style context.
3. Hard: Evaluate, prove, compare or justify a response to Components of a Computer: Processor Components, using evidence and a final judgement where relevant.
4. Retrieval: Write one misconception a student might have about Components of a Computer: Processor Components, then correct it in mark-scheme language.

When reviewing MCQs, do not just record the correct option. Record the misconception behind each wrong option so Proof Coach can turn the mistake into a targeted repair task.

Proof Coach hooks

If this topic appears in your dashboard, Proof Coach should track:

• technical precision
• algorithm trace
• solution design
• evaluation evidence